Mobile communication devices may include a variety of components including circuit boards, integrated circuit (IC) devices and/or System-on-Chip (SoC) devices. The components may include processing circuits, user interface components, storage and other peripheral components that communicate through a serial bus. The serial bus may be operated in accordance with a standardized or proprietary protocol.
In one example, a serial bus operated in accordance with an Inter-Integrated Circuit (I2C bus or I2C) is a serial single-ended computer bus that was intended for use in connecting low-speed peripherals to a processor. In some examples, a serial bus may employ a multi-master protocol in which one or more devices can serve as a master and a slave for different messages transmitted on the serial bus. Data can be serialized and transmitted over two bidirectional wires, which may carry a data signal, which may be carried on a Serial Data Line (SDA), and a clock signal, which may be carried on a Serial Clock Line (SCL).
In another example, Improved Inter-Integrated Circuit (I3C) protocols may be used to control operations on a serial bus. The I3C protocols are defined by the Mobile Industry Processor Interface Alliance (MIPI) and derive certain implementation aspects from the I2C protocol. Original implementations of the I2C protocol supported data signaling rates of up to 100 kilobits per second (100 kbps) in standard-mode operation, with more recent standards supporting speeds of 400 kbps in fast-mode operation, and 1 megabit per second (Mbps) in fast-mode plus operation.
As applications have become more complex, it has become desirable to couple devices with widely varying response times and latencies to a common serial bus. Conventional I3C protocols require slave devices that are not capable of responding to read commands within one cycle of the bus clock signal to respond to the read command with a negative acknowledgement (NACK), and necessitate that the master device issuing the read command repeat the read command thereby causing longer read times. Complexity of slave device design is increased in order to respond to the repeated read command. In many conventional implementations, the slave must be equipped with, and must manage, a small cache storage that holds the content of the register identified in the initial read command to respond to the command when repeated.